2.1. Types

This document refers to integer types with the notation SN to specify a type's signedness (S) and bit width (N), respectively.¶

For example, u32 is a type whose valid values are all the 32-bit unsigned numbers and s16 is a type whose valid values are all the 16-bit signed numbers.¶

2.2. Functions

The following byte swap functions are direction agnostic. That is, the same function is used for conversion in either direction discussed below.¶

• be16: Takes an unsigned 16-bit number and converts it between host byte order and big-endian byte order [IEN137].¶
• be32: Takes an unsigned 32-bit number and converts it between host byte order and big-endian byte order.¶
• be64: Takes an unsigned 64-bit number and converts it between host byte order and big-endian byte order.¶
• bswap16: Takes an unsigned 16-bit number in either big- or little-endian format and returns the equivalent number with the same bit width but opposite endianness.¶
• bswap32: Takes an unsigned 32-bit number in either big- or little-endian format and returns the equivalent number with the same bit width but opposite endianness.¶
• bswap64: Takes an unsigned 64-bit number in either big- or little-endian format and returns the equivalent number with the same bit width but opposite endianness.¶
• le16: Takes an unsigned 16-bit number and converts it between host byte order and little-endian byte order.¶
• le32: Takes an unsigned 32-bit number and converts it between host byte order and little-endian byte order.¶
• le64: Takes an unsigned 64-bit number and converts it between host byte order and little-endian byte order.¶

2.3. Definitions

Sign Extend:

To sign extend an X-bit number, A, to a Y-bit number, B, means to¶

1. Copy all X bits from A to the lower X bits of B.¶
2. Set the value of the remaining Y - X bits of B to the value of the most significant bit of A.¶

2.4. Conformance Groups

An implementation does not need to support all instructions specified in this document (e.g., deprecated instructions). Instead, a number of conformance groups are specified. An implementation MUST support the base32 conformance group and MAY support additional conformance groups, where supporting a conformance group means it MUST support all instructions in that conformance group.¶

The use of named conformance groups enables interoperability between a runtime that executes instructions, and tools such as compilers that generate instructions for the runtime. Thus, capability discovery in terms of conformance groups might be done manually by users or automatically by tools.¶

Each conformance group has a short ASCII label (e.g., "base32") that corresponds to a set of instructions that are mandatory. That is, each instruction has one or more conformance groups of which it is a member.¶

This document defines the following conformance groups:¶

base32:

includes all instructions defined in this specification unless otherwise noted.¶

base64:

includes base32, plus instructions explicitly noted as being in the base64 conformance group.¶

atomic32:

includes 32-bit atomic operation instructions (see Section 5.3).¶

atomic64:

includes atomic32, plus 64-bit atomic operation instructions.¶

divmul32:

includes 32-bit division, multiplication, and modulo instructions.¶

divmul64:

includes divmul32, plus 64-bit division, multiplication, and modulo instructions.¶

packet:

deprecated packet access instructions.¶

3.1. Basic Instruction Encoding

A basic instruction is encoded as follows:¶

+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|    opcode     |     regs      |            offset             |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|                              imm                              |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+

opcode:

operation to perform, encoded as follows:¶

+-+-+-+-+-+-+-+-+
|specific |class|
+-+-+-+-+-+-+-+-+

¶

specific:

The format of these bits varies by instruction class¶

class:

the instruction class (see Section 3.3)¶

regs:

the source and destination register numbers, encoded as follows on a little-endian host:¶

+-+-+-+-+-+-+-+-+
|src_reg|dst_reg|
+-+-+-+-+-+-+-+-+

¶

and as follows on a big-endian host:¶

+-+-+-+-+-+-+-+-+
|dst_reg|src_reg|
+-+-+-+-+-+-+-+-+

¶

src_reg:

the source register number (0-10), except where otherwise specified (64-bit immediate instructions (see Section 5.4) reuse this field for other purposes)¶

dst_reg:

the destination register number (0-10), unless otherwise specified (future instructions might reuse this field for other purposes)¶

offset:

signed integer offset used with pointer arithmetic, except where otherwise specified (some arithmetic instructions reuse this field for other purposes)¶

imm:

signed integer immediate value¶

Note that the contents of multi-byte fields ('offset' and 'imm') are stored using big-endian byte ordering on big-endian hosts and little-endian byte ordering on little-endian hosts.¶

For example:¶

opcode                  offset imm          assembly
       src_reg dst_reg
07     0       1        00 00  44 33 22 11  r1 += 0x11223344 // little
       dst_reg src_reg
07     1       0        00 00  11 22 33 44  r1 += 0x11223344 // big

Note that most instructions do not use all of the fields. Unused fields SHALL be cleared to zero.¶

3.2. Wide Instruction Encoding

Some instructions are defined to use the wide instruction encoding, which uses two 32-bit immediate values. The 64 bits following the basic instruction format contain a pseudo instruction with 'opcode', 'dst_reg', 'src_reg', and 'offset' all set to zero.¶

This is depicted in the following figure:¶

+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|    opcode     |     regs      |            offset             |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|                              imm                              |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|                           reserved                            |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|                           next_imm                            |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+

opcode:

operation to perform, encoded as explained above¶

regs:

the source and destination register numbers (unless otherwise specified), encoded as explained above¶

offset:

signed integer offset used with pointer arithmetic, unless otherwise specified¶

imm:

signed integer immediate value¶

reserved:

unused, set to zero¶

next_imm:

second signed integer immediate value¶

3.3. Instruction Classes

The three least significant bits of the 'opcode' field store the instruction class:¶

4.1. Arithmetic Instructions

ALU uses 32-bit wide operands while ALU64 uses 64-bit wide operands for otherwise identical operations. ALU64 instructions belong to the base64 conformance group unless noted otherwise. The 'code' field encodes the operation as below, where 'src' refers to the source operand and 'dst' refers to the value of the destination register.¶

Underflow and overflow are allowed during arithmetic operations, meaning the 64-bit or 32-bit value will wrap. If BPF program execution would result in division by zero, the destination register is instead set to zero. If execution would result in modulo by zero, for ALU64 the value of the destination register is unchanged whereas for ALU the upper 32 bits of the destination register are zeroed.¶

{ADD, X, ALU}, where 'code' = ADD, 'source' = X, and 'class' = ALU, means:¶

   dst = (u32) ((u32) dst + (u32) src)

where '(u32)' indicates that the upper 32 bits are zeroed.¶

{ADD, X, ALU64} means:¶

   dst = dst + src

{XOR, K, ALU} means:¶

   dst = (u32) dst ^ (u32) imm

{XOR, K, ALU64} means:¶

   dst = dst ^ imm

Note that most arithmetic instructions have 'offset' set to 0. Only three instructions (SDIV, SMOD, MOVSX) have a non-zero 'offset'.¶

Division, multiplication, and modulo operations for ALU are part of the "divmul32" conformance group, and division, multiplication, and modulo operations for ALU64 are part of the "divmul64" conformance group. The division and modulo operations support both unsigned and signed flavors.¶

For unsigned operations (DIV and MOD), for ALU, 'imm' is interpreted as a 32-bit unsigned value. For ALU64, 'imm' is first sign extended (Section 2.3) from 32 to 64 bits, and then interpreted as a 64-bit unsigned value.¶

For signed operations (SDIV and SMOD), for ALU, 'imm' is interpreted as a 32-bit signed value. For ALU64, 'imm' is first sign extended (Section 2.3) from 32 to 64 bits, and then interpreted as a 64-bit signed value.¶

Note that there are varying definitions of the signed modulo operation when the dividend or divisor are negative, where implementations often vary by language such that Python, Ruby, etc. differ from C, Go, Java, etc. This specification requires that signed modulo MUST use truncated division (where -13 % 3 == -1) as implemented in C, Go, etc.:¶

   a % n = a - n * trunc(a / n)

The MOVSX instruction does a move operation with sign extension. {MOVSX, X, ALU} sign extends (Section 2.3) 8-bit and 16-bit operands into 32-bit operands, and zeroes the remaining upper 32 bits. {MOVSX, X, ALU64} sign extends (Section 2.3) 8-bit, 16-bit, and 32-bit operands into 64-bit operands. Unlike other arithmetic instructions, MOVSX is only defined for register source operands (X).¶

{MOV, K, ALU64} means:¶

   dst = (s64)imm

{MOV, X, ALU} means:¶

   dst = (u32)src

{MOVSX, X, ALU} with 'offset' 8 means:¶

   dst = (u32)(s32)(s8)src

The NEG instruction is only defined when the source bit is clear (K).¶

Shift operations use a mask of 0x3F (63) for 64-bit operations and 0x1F (31) for 32-bit operations.¶

4.2. Byte Swap Instructions

The byte swap instructions use instruction classes of ALU and ALU64 and a 4-bit 'code' field of END.¶

The byte swap instructions operate on the destination register only and do not use a separate source register or immediate value.¶

For ALU, the 1-bit source operand field in the opcode is used to select what byte order the operation converts from or to. For ALU64, the 1-bit source operand field in the opcode is reserved and MUST be set to 0.¶

The 'imm' field encodes the width of the swap operations. The following widths are supported: 16, 32, and 64. Width 64 operations belong to the base64 conformance group and other swap operations belong to the base32 conformance group.¶

Examples:¶

{END, LE, ALU} with 'imm' = 16/32/64 means:¶

   dst = le16(dst)
   dst = le32(dst)
   dst = le64(dst)

{END, BE, ALU} with 'imm' = 16/32/64 means:¶

   dst = be16(dst)
   dst = be32(dst)
   dst = be64(dst)

{END, TO, ALU64} with 'imm' = 16/32/64 means:¶

   dst = bswap16(dst)
   dst = bswap32(dst)
   dst = bswap64(dst)

4.3. Jump Instructions

JMP32 uses 32-bit wide operands and indicates the base32 conformance group; JMP uses 64-bit wide operands for otherwise identical operations and indicates the base64 conformance group unless otherwise specified. The 'code' field encodes the operation as below:¶

where 'PC' denotes the program counter, and the offset to increment by is in units of 64-bit instructions relative to the instruction following the jump instruction. Thus 'PC += 1' skips execution of the next instruction if it's a basic instruction or results in undefined behavior if the next instruction is a 128-bit wide instruction.¶

Example:¶

{JSGE, X, JMP32} means:¶

   if (s32)dst s>= (s32)src goto +offset

where 's>=' indicates a signed '>=' comparison.¶

{JLE, K, JMP} means:¶

   if dst <= (u64)(s64)imm goto +offset

{JA, K, JMP32} means:¶

   gotol +imm

where 'imm' means the branch offset comes from the 'imm' field.¶

Note that there are two flavors of JA instructions. The JMP class permits a 16-bit jump offset specified by the 'offset' field, whereas the JMP32 class permits a 32-bit jump offset specified by the 'imm' field. A conditional jump greater than 16 bits may be converted to a conditional jump less than 16 bits plus a 32-bit unconditional jump.¶

All CALL and JA instructions belong to the base32 conformance group.¶

5.1. Regular Load and Store Operations

The MEM mode modifier is used to encode regular load and store instructions that transfer data between a register and memory.¶

{MEM, <size>, STX} means:¶

   *(size *) (dst + offset) = src

{MEM, <size>, ST} means:¶

   *(size *) (dst + offset) = imm

{MEM, <size>, LDX} means:¶

   dst = *(unsigned size *) (src + offset)

Where '<size>' is one of: B, H, W, or DW, and 'unsigned size' is one of: u8, u16, u32, or u64.¶

5.2. Sign-Extension Load Operations

The MEMSX mode modifier is used to encode sign-extension load instructions (Section 2.3) that transfer data between a register and memory.¶

{MEMSX, <size>, LDX} means:¶

   dst = *(signed size *) (src + offset)

Where '<size>' is one of: B, H, or W, and 'signed size' is one of: s8, s16, or s32.¶

5.3. Atomic Operations

Atomic operations operate on memory and cannot be interrupted or corrupted by other access to the same memory region by other BPF programs or means outside of this specification.¶

All atomic operations supported by BPF are encoded as store operations that use the ATOMIC mode modifier as follows:¶

• {ATOMIC, W, STX} for 32-bit operations, which are part of the "atomic32" conformance group.¶
• {ATOMIC, DW, STX} for 64-bit operations, which are part of the "atomic64" conformance group.¶
• 8-bit and 16-bit wide atomic operations are not supported.¶

The 'imm' field is used to encode the actual atomic operation. Simple atomic operations use a subset of the values defined to encode arithmetic operations in the 'imm' field to encode the atomic operation:¶

{ATOMIC, W, STX} with 'imm' = ADD means:¶

   *(u32 *)(dst + offset) += src

{ATOMIC, DW, STX} with 'imm' = ADD means:¶

   *(u64 *)(dst + offset) += src

In addition to the simple atomic operations, there is also a modifier and two complex atomic operations:¶

The FETCH modifier is optional for simple atomic operations and is always set for the complex atomic operations. If the FETCH flag is set, then the operation also overwrites src with the value that was in memory before it was modified.¶

The XCHG operation atomically exchanges src with the value addressed by dst + offset.¶

The CMPXCHG operation atomically compares the value addressed by dst + offset with R0. If they match, the value addressed by dst + offset is replaced with src. In either case, the value that was at dst + offset before the operation is zero-extended and loaded back to R0.¶

5.4. 64-bit Immediate Instructions

Instructions with the IMM 'mode' modifier use the wide instruction encoding defined in Section 3, and use the 'src_reg' field of the basic instruction to hold an opcode subtype.¶

The following table defines a set of {IMM, DW, LD} instructions with opcode subtypes in the 'src_reg' field, using new terms such as "map" defined further below:¶

where¶

• map_by_fd(imm) means to convert a 32-bit file descriptor into an address of a map (see Section 5.4.1)¶
• map_by_idx(imm) means to convert a 32-bit index into an address of a map¶
• map_val(map) gets the address of the first value in a given map¶
• var_addr(imm) gets the address of a platform variable (see Section 5.4.2) with a given id¶
• code_addr(imm) gets the address of the instruction at a specified relative offset in number of (64-bit) instructions¶
• the 'imm type' can be used by disassemblers for display¶
• the 'dst type' can be used for verification and just-in-time compilation purposes¶

5.5. Legacy BPF Packet Access Instructions

BPF previously introduced special instructions for access to packet data that were carried over from classic BPF. These instructions used an instruction class of LD, a size modifier of W, H, or B, and a mode modifier of ABS or IND. The 'dst_reg' and 'offset' fields were set to zero, and 'src_reg' was set to zero for ABS. However, these instructions are deprecated and SHOULD no longer be used. All legacy packet access instructions belong to the "packet" conformance group.¶

7.1. BPF Instruction Conformance Groups Registry

This document defines an IANA registry for BPF instruction conformance groups, as follows:¶

• Name of the registry: BPF Instruction Conformance Groups¶
• Name of the registry group: BPF Instructions¶
• Required information for registrations: See the BPF Instruction Conformance Groups Registration Template (Section 7.1.1)¶
• Syntax of registry entries: Each entry has the following fields: name, description, includes, excludes, status, change controller, and reference. See Section 7.1.1 for more details.¶

• Registration policy (see Section 4 of [RFC8126] for details):¶

  • Permanent: Standards Action or IESG Approval¶
  • Provisional: Specification Required¶
  • Historical: Specification Required¶
• Contact: BPF Working Group¶
• Change Controller: IETF¶

Initial entries in this registry are as follows:¶

7.2. BPF Instruction Set Registry

This document defines an IANA registry for BPF instructions, as follows:¶

• Name of the registry: BPF Instruction Set¶
• Name of the registry group: BPF Instructions¶
• Required information for registrations: See the BPF Instruction Registration Template (Section 7.2.1)¶
• Syntax of registry entries: Each entry has the following fields: opcode, src, offset, imm, description, groups, change controller, and reference. See Section 7.2.1 for more details.¶
• Registration policy: New instructions require a new entry in the conformance group registry and the same registration policies apply.¶
• Contact: BPF Working Group¶
• Change Controller: IETF¶
• Initial registrations: See Appendix A. Instructions other than those listed as deprecated are Permanent. Any listed as deprecated are Historical.¶

7.3. Adding Instructions

A specification may add additional instructions to the BPF Instruction Set registry. Once a conformance group is registered with a set of instructions, no further instructions can be added to that conformance group. A specification should instead create a new conformance group that includes the original conformance group, plus any newly added instructions. Inclusion of the original conformance group is done via the "includes" column of the BPF Instruction Conformance Groups registry, and inclusion of newly added instructions is done via the "groups" column of the BPF Instruction Set registry.¶

For example, consider an existing hypothetical group called "example" with two instructions in it. One might add two more instructions by first adding an "examplev2" group to the BPF Instruction Conformance Groups registry as follows:¶

And then adding the new instructions into the BPF Instruction Set registry as follows:¶

Supporting the "examplev2" group thus requires supporting all four example instructions.¶

7.4. Deprecating Instructions

Deprecating instructions that are part of an existing conformance group can be done by defining a new conformance group for the newly deprecated instructions, and defining a new conformance group that supersedes the existing conformance group containing the instructions, where the new conformance group includes the existing one and excludes the deprecated instruction group.¶

For example, if deprecating an instruction in an existing hypothetical group called "example", two new groups ("legacyexample" and "examplev2") might be registered in the BPF Instruction Conformance Groups registry as follows:¶

The BPF Instruction Set registry entries for the deprecated instructions would then be updated to add "legacyexample" to the set of groups for those instructions, as follows:¶

Finally, updated implementations that dropped support for the deprecated instructions would then be able to claim conformance to "examplev2" rather than "example".¶

7.5. Change Control

Registrations can be updated in a registry by the same mechanism as required for an initial registration. In cases where the original definition of an entry is contained in an IESG-approved document, in which case the IETF would be the change controller, update of the specification also requires IESG approval.¶

'Provisional' registrations can be updated by the change controller designated in the existing registration. In addition, the IESG can reassign responsibility for a 'Provisional' registration or can request specific changes to an entry. This will enable changes to be made to entries where the original registrant is out of contact or unwilling or unable to make changes.¶

Transition from 'Provisional' to 'Permanent' status can be requested and approved in the same manner as a new 'Permanent' registration. Transition from 'Permanent' to 'Historical' status requires IESG approval. Transition from 'Provisional' to 'Historical' can be requested by anyone authorized to update the 'Provisional' registration.¶

7.6. Expert Review Instructions

The IANA registries established by this document are informed by written specifications, which themselves are facilitated and approved by an Expert Review process (see Section 5.3 of [RFC8126]).¶

Designated experts are expected to consult with the active BPF working group (e.g., via email to the working group's mailing list) if it exists, as well as other interested parties (e.g., via email to one or more active mailing list(s) for relevant BPF communities and platforms). The designated expert is expected to verify that the encoding and semantics for any new instructions are properly documented in a public-facing specification. In the event of future RFC documents for ISA extensions, experts may permit early assignment before the RFC document is available, as long as a specification that satisfies the above requirements exists.¶